Multi-chip electronic components typically include two or more semiconductor components which are mounted adjacent to one another on a die pad. For multi-chip modules including vertical power MOSFET devices, the electrical performance of the module is dependent on the area or lateral dimensions of the MOSFET devices. Consequently, the electrical performance of the module is dependent on the desired size of the package, since the size of the package limits the lateral size of the die pad which in turn defines the maximum area available for the devices.
In practice, the maximum possible lateral area of the devices is less than the area of the die pad since an area around the semiconductor device is left unoccupied to accommodate the so-called “solder splash”. The semiconductor components are typically mounted on the die pad by providing a soft solder deposit on the die pad and pressing the semiconductor component into the soft solder deposit. Consequently, solder is pushed from the area underneath the semiconductor component into adjacent regions, the so called “solder splash”. This spreading of the soft solder deposit limits the area available for the semiconductor components within the area of the die pad. Therefore, the electrical properties achievable within a package of a certain size is limited.
A further problem associated with the spread of the solder deposit may occur if a multi-step die attach method is used. During the attachment of a second or subsequent die, the soft solder attaching the first die remelts. This can result in movement of the first die, particularly if the two solder deposits bridge to form a single solder deposit. Due to the different sizes of the semiconductor components, the components may sink into the solder deposit by different amounts so that the upper surfaces of the components lie in different planes and may lie at inclined angle to the die pad. This is disadvantageous as the contact areas may not lie in the desired position and, consequently, the wire bonds may not be formed correctly from the components to the leadframe or rewiring structure of the electronic component.
To overcome these problems, it is known to use a larger die pad and consequently a larger package if the area of the semiconductor components is to be increased. However, a larger package is often undesired due to the increasing demands for miniaturization of electronic components along with the demand for increased performance for a package of a given size.
There is a need for an electronic component which is able to accommodate semiconductor components of a larger lateral area so as to provide an improved electrical performance within a defined package footprint.
There is also a need to provide methods by which an electronic component with an increased area of semiconductor components may be cost-effectively manufactured.